preliminary 512k level ii extended cache module cym74p435 cypress semiconductor corporation ? 3901 north first street san jose ca 95134 408-943-2600 document #: 38-05007 rev. ** revised april 25, 2001 features ? 512k cache module with extended cache ability synchronous configuration with presence and configuration detect pins 66 mhz operation uses high-performance synchronous srams 160-position burndy dimm celp2x80sc3z48 connector 3.3v compatible inputs/data outputs functional description this family of secondary cache modules is designed for intel p54c systems with the 82430fx (triton) chipset. the cym74p435 is a 512-kb module, organized as 64k by 64-bits with two 32kx8 tag rams that supports 3-1-1-1 read and 4-2-2-2 write cycles at cpu bus speeds up to 66 mhz. the synchronous modules are available with low cost synchro- nous pipelined rams. the synchronous pipelined modules are based on a 64k x 32 ram. multiple ground pins and on-board decoupling capacitors ensure high performance with maximum noise immunity. all components on the cache modules are surface mounted on a multi-layer epoxy laminate (fr-4) substrate. the contact pins are plated with 150 micro-inches of nickel covered by 10 micro-inches of gold flash. intel is a registered trademark of intel corporation logic block diagram - cym74p435 we0/1 we2/3 a d d ce ce oe ccs coe cwe [7:0] a a[18:3] adv adv adv adsc adsc adsc adsc adsc adsp adsp adsp clk0 d[63:32] d[31:0] d[63:0] tio[7:0] a[18:5] twe d oe oe ce we gnd 32kx8 gnd gnd gnd a(18:5) we ce oe d tio[10:8]
cym74p435 preliminary document #: 38-05007 rev. ** page 2 of 6 part number 74p435-66 cache size ram type 512k system clock (mhz) 66 data t cdv 8.5 ns tag t aa 15 ns
cym74p435 preliminary document #: 38-05007 rev. ** page 3 of 6 pin configuration top view dual read-out simm (dimm) 10 9 5 6 7 8 4 1 2 gnd d 63 gnd d 62 nc d 58 d 54 v cc d 61 v cc d 59 d 55 d 57 gnd d 56 d 60 3 90 89 85 86 87 88 84 81 82 83 20 19 15 16 17 18 14 11 12 d 52 d 50 d 46 d 44 gnd d 42 gnd d 48 13 30 29 25 26 27 28 24 21 22 d 38 d 36 d 32 d 30 d 26 d 24 gnd d 28 d 34 gnd 23 39 35 36 37 38 34 31 32 d 22 nc gnd d 14 d 12 d 16 d 20 33 40 41 42 gnd d 10 52 51 47 48 49 50 46 43 44 d 8 d 6 d 4 d 0 gnd a 3 d 2 45 57 58 59 60 56 53 54 a 5 gnd a 7 55 69 65 66 67 68 64 61 62 gnd cwe 6 cwe 4 gnd 63 70 79 75 76 77 78 74 71 72 cwe 2 cwe 0 73 80 d 53 d 51 gnd d 49 d 47 d 45 d 41 d 43 100 99 95 96 97 98 94 91 92 93 d 39 d 37 d 35 d 33 d 31 d 25 d 29 d 27 110 109 105 106 107 108 104 101 102 103 d 23 d 21 v cc d 19 d 15 d 13 d 17 120 119 115 116 117 118 114 111 112 113 d 11 121 122 v cc d 9 d 7 d 5 d 3 d 1 127 128 129 130 126 123 124 125 gnd a 6 a 4 gnd 140 139 135 136 137 138 134 131 132 133 gnd pd 0 cwe 5 caa 4 150 149 145 146 147 148 144 141 142 143 gnd gnd v cc 160 159 155 156 157 158 154 151 152 153 tio 0 tio 2 tio 6 tio 4 tio8 twe caa 3 nc nc nc a 11 a 16 nc a 12 a 13 nc cs nc pd 1 pd 3 d 40 d 18 gnd tio 1 tio 7 tio 5 tio 3 tio9 tio10 coe cwe 7 cwe 1 cwe 3 cab 3 cale rsvd a 8 a 10 a 17 a 9 a 14 a 15 rsvd pd 2 pd 4 nc gnd gnd v cc v cc gnd v cc gnd nc nc nc nc nc nc nc 74b435 ? 5
cym74p435 preliminary document #: 38-05007 rev. ** page 4 of 6 pin definitions common signals description v cc 3.3v supply gnd ground a[18:3] addresses from processor coe output enable cwe [7:0] byte write enables pd 0 -pd 4 presence detect output pins d[63:0] data lines from processor tio[10:0] tag data bits twe tag write enable signal nc signal not connected on module rsvd reserved v ccq 3.3v supply adsp processor address strobe adsc cache controller address strobe adv burst address advance ccs chip select clk[1:0] clock signals, clk1 not used on cym74p435 presence detect pins pd 4 pd 3 pd 2 pd 1 pd 0 synchronous burst - cym74p435 nc gnd gnd nc gnd
cym74p435 preliminary document #: 38-05007 rev. ** page 5 of 6 ? cypress semiconductor corporation, 2001. the information contained herein is subject to change without notice. cypress semico nductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress semiconductor product. nor does it convey or imply any license unde r patent or other rights. cypress semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected t o result in significant injury to the user. the inclusion of cypress semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in do i ng so indemnifies cypress semiconductor against all charges. maximum ratings (above which the useful life may be impaired. for user guide- lines, not tested.) storage temperature ? 55 c to +125 c ambient temperature with power applied ? 0 c to +70 c 3.3v supply voltage to ground potential ? 0.5v to +5.25v 5v supply voltage to ground potential ? 0.5v to +5.25v dc voltage applied to outputs in high z state ? 0.5v to +4.6v dc input voltage ? 0.5v to +4.6v output current into outputs (low)20 ma operating range range ambient tempera- ture v cc v ccq commercial 0 c to +70 c 3.3v 10% 3.3v/2.5v +/- 10% electrical characteristics over the operating range parameter description test condition min. max. unit v ih input high voltage 2.2 v cc + 0.3 v v il input low voltage ? 0.3 0.8 v v oh output high voltage v cc = min. i oh = ? 4 ma 2.4 v v ol output low voltage v cc = min. i ol = 8 ma 0.4 v i cc (74p435) v cc operating supply current v cc = max., i out = 0 ma, f = f max = 1/t rc 1400 ma ordering information speed (mhz) ordering code package name package type description operating range 66 cym74p435cpm-66c pm49 160-pin dual read-out s(d)imm sync pipelined 512 kb commercial package diagrams 160-pin dual read-out s(d)imm pm49
cym74p435 preliminary document #: 38-05007 rev. ** page 6 of 6 document title: cym74p435 512 level ii extended cache module document number: 38-05007 rev. ecn no. issue date orig. of change description of change ** 106010 05/07/01 meg new spec
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